1. Field of the Invention
This invention relates to the field of multiprocessor computer systems and, more particularly, to storing coherency states within multiple subnodes of processing nodes in distributed shared memory multiprocessing computer systems.
2. Description of the Relevant Art
Multiprocessing computer systems include two or more processors which may be employed to perform computing tasks. A particular computing task may be performed upon one processor while other processors perform unrelated computing tasks. Alternatively, components of a particular computing task may be distributed among multiple processors to decrease the time required to perform the computing task as a whole. Generally speaking, a processor is a device configured to perform an operation upon one or more operands to produce a result. The operation is performed in response to an instruction executed by the processor.
A popular architecture in commercial multiprocessing computer systems is the symmetric multiprocessor (SMP) architecture. Typically, an SMP computer system comprises multiple processors connected through a cache hierarchy to a shared bus. Additionally connected to the bus is a memory, which is shared among the processors in the system. Access to any particular memory location within the memory occurs in a similar amount of time as access to any other particular memory location. Since each location in the memory may be accessed in a uniform manner, this structure is often referred to as a uniform memory architecture (UMA).
Processors are often configured with internal caches, and one or more caches are typically included in the cache hierarchy between the processors and the shared bus in an SMP computer system. Multiple copies of data residing at a particular main memory address may be stored in these caches. In order to maintain the shared memory model, in which a particular address stores exactly one data value at any given time, shared bus computer systems employ cache coherency. Generally speaking, an operation is coherent if the effects of the operation upon data stored at a particular memory address are reflected in each copy of the data within the cache hierarchy. For example, when data stored at a particular memory address is updated, the update may be supplied to the caches which are storing copies of the previous data. Alternatively, the copies of the previous data may be invalidated in the caches such that a subsequent access to the particular memory address causes the updated copy to be transferred from main memory. For shared bus systems, a snoop bus protocol is typically employed. Each coherent transaction performed upon the shared bus is examined (or "snooped") against data in the caches. If a copy of the affected data is found, the state of the cache line containing the data may be updated in response to the coherent transaction.
Unfortunately, shared bus architectures suffer from several drawbacks which limit their usefulness in multiprocessing computer systems. A bus is capable of a peak bandwidth (e.g. a number of bytes/second which may be transferred across the bus). As additional processors are attached to the bus, the bandwidth required to supply the processors with data and instructions may exceed the peak bus bandwidth. Since some processors are forced to wait for available bus bandwidth, performance of the computer system suffers when the bandwidth requirements of the processors exceeds available bus bandwidth.
Additionally, adding more processors to a shared bus increases the capacitive loading on the bus and may even cause the physical length of the bus to be increased. The increased capacitive loading and extended bus length increases the delay in propagating a signal across the bus. Due to the increased propagation delay, transactions may take longer to perform. Therefore, the peak bandwidth of the bus may decrease as more processors are added.
These problems are further magnified by the continued increase in operating frequency and performance of processors. The increased performance enabled by the higher frequencies and more advanced processor microarchitectures results in higher bandwidth requirements than previous processor generations, even for the same number of processors. Therefore, buses which previously provided sufficient bandwidth for a multiprocessing computer system may be insufficient for a similar computer system employing the higher performance processors.
Another structure for multiprocessing computer systems is a distributed shared memory architecture. A distributed shared memory architecture includes multiple nodes within which processors and memory reside. The multiple nodes communicate via a network coupled there between. When considered as a whole, the memory included within the multiple nodes forms the shared memory for the computer system. Typically, directories are used to identify which nodes have cached copies of data corresponding to a particular address. Coherency activities may be generated via examination of the directories.
Distributed shared memory systems are scaleable, overcoming the limitations of the shared bus architecture. Since many of the processor accesses are completed within a node, nodes typically have much lower bandwidth requirements upon the network than a shared bus architecture must provide upon its shared bus. The nodes may operate at high clock frequency and bandwidth, accessing the network when needed. Additional nodes may be added to the network without affecting the local bandwidth of the nodes. Instead, only the network bandwidth is affected.
Many distributed shared memory systems suffer from a limitation upon the memory which may be included within a node. The limitation arises not from the number of memory modules (such as dynamic random access memory, or DRAM, modules which are popular in the industry) which may be configured into a node to form the memory, but instead arises from the amount of memory which may be used to store the access rights of the node to a particular coherency unit within the memory. In order to maintain system-wide memory coherency, the access rights granted to a particular node must be respected by that node. However, the node typically employs high speed internal communications, such that the access rights must by accessible very quickly. DRAM is typically not suitable for high speed access. Instead, static random access memory (SRAM) modules are typically used to store the access rights.
While SRAM modules may respond with speeds suitable for use in storing access rights, SRAM modules suffer from other drawbacks. SRAM modules are not fabricated with the densities typified by DRAM. In other words, a much larger number of SRAM modules must be used to store the same number of bits as a particular number of DRAM modules. Unfortunately, the lack of density in SRAM modules leads to increased pinouts on modules housing the control logic which interfaces to the SRAM modules in order to store, retrieve, and analyze access rights corresponding to a coherency unit accessed by a transaction occurring within the node. The number of SRAM modules which may be used is therefore limited by the number of pins available on the control logic modules. Hence, the number of access rights (and therefore the number of coherency units) which may be stored in the node is limited. Additionally, SRAM modules are significantly more expensive then DRAM modules. In order to minimize the cost of the computer system, it is important to minimize the number of SRAM modules included.
For at least the above reasons, the amount of memory needed to store access rights may limit the amount of main memory which may be included within the node. Still further, if less than the maximum amount of memory is included in a node, it is desirable to reduce the memory dedicated to storing access rights accordingly. In addition, it is desirable to be able to upgrade the amount of memory in a given node subsequent to manufacture of the computer system. Therefore, the amount of memory used for storing access rights must be similarly increasable.